(1) Field of the Invention
The present invention relates to the manufacturing of semiconductor memories, and in particular, is directed to a stacked-gate flash memory having a step-shaped floating polysilicon gate to improve its program speed, and also to a method of forming the same.
(2) Description of the Related Art
The higher the capacitive coupling between the floating gate and the control gate of a conventional stacked-gate memory cell, the higher is the program speed of the cell, as is well-known in the art. Capacitive coupling can be increased by increasing the capacitance, through an increase in the areas of the floating and control gate electrodes. On the contrary, however, because of the continued downscaling in the ultra large scale integration of semiconductor devices in general, the cell area, and hence the areas of the gate electrodes are necessarily being reduced. As a result, it has been difficult to maintain the same coupling levels, let alone increasing them. It is disclosed in the present invention a method of increasing the areas of the gate electrodes, without increasing the cell size, and hence that of the inter-dielectric layer between the gates. The coupling ratio, defined as the ratio of the area of the inter-dielectric layer to the area of the tunnel dielectric layer between the substrate and the floating gate is also increased, yielding a high program and erase speed for the stacked-gate memory cell, as described more fully below.
Although higher coupling ratios between the control gate and the floating gate can be supported by thinner inter-gate dielectric layers, or, inter-polygate oxides, data retention can cause concern due to leakages from thin layers. Also, word line voltages on control gates can be increased to increase programming and erase speeds. But, without the supporting larger area, which is provided in this invention, the situation exacerbates the well-known problem of junction break-down. It is shown later in the embodiments of this invention that larger areas can be achieved by forming gates with multiply connected surfaces of different shapes.
The importance of data retention capacity and the coupling ratio in a memory cell has been well recognized since the advent of the one-transistor cell memory cell with one capacitor. Over the years, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improving its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMS) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Generally, flash EEPROM cells having both functions of electrical programming and erasing may be classified into two categories, namely, a stacked-gate structure and a split-gate structure not discussed here. A conventional stacked-gate type cell is shown in FIG. 1 where, as is well known, tunnel oxide film (20), a floating gate (30), an interpoly insulating film (40) and a control gate (50) are sequentially stacked on a silicon substrate (10) between a drain region (13) and a source region (15) separated by channel region (17). Substrate (10) and channel region (17) are of a first conductivity type, and the first (13) and second (15) doped regions are of a second conductivity type that is opposite the first conductivity type.
The programming and erasing of the flash EEPROM shown in FIG. 1 is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling, as it is known in the art. Basically, a sufficiently high voltage is applied to control gate (50) and drain (13) while source (15) is grounded to create a flow of electrons in channel region (17) in substrate (10). Some of these electrons gain enough energy to transfer from the substrate to control gate (50) through thin gate oxide layer (20) by means of (F-N) tunneling. The tunneling is achieved by raising the voltage level on control gate (50) to a sufficiently high value of about 12 volts. As the electronic charge builds up on floating gate (30), the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, floating gate (30) remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, floating gate (30) can be erased by grounding control gate (50) and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate.
The thicknesses of the various portions of the oxide layers on the stacked-gate flash memory cell of FIG. 1 play an important role in determining such parameters as current consumption, coupling ratio and the memory erase-write speed, especially in an environment where feature sizes in advanced integrated circuits are being scaled down at a rapid rate. In prior art, various methods have been developed to address these parameters. For example, EPROMs having a trench-like coupling capacitors have been disclosed to address the shrinking area of the gate electrodes, and hence the capacitive coupling ratio between the floating gate and control gates on a conventional prior art EPROM. In U.S. Pat. No. 5,801,415, Lee, et al., teach a method for making a such a trench-like coupling capacitor in a non-volatile memory cell from a single filed-effect transistor (FET) that incorporates a floating gate over the FET channel area. The floating gate also extends vertically upward on the sidewalls of the control gate, thereby increasing the capacitor area between the floating and control gates. Tseng of U.S. Pat. No. 5,677,216 also utilizes a trench with a floating gate so as to increase the surface area of the inter-poly in order to achieve a higher coupling ratio.
On the other hand, Tseng uses a different structure in U.S. Pat. No. 5,451,537 in forming a stack capacitor in a dynamic random access memory cell. Here, a bottom electrode is connected to an extends up from the source region of a MOS transistor, and has a top surface with a central cavity, and side surfaces extending down from the top surface in a step-like, or ladder, manner. These step-like sides are formed by a repeated tow-step process of removing a portion of the vertical walls of a photoresist mask and removing a portion of the top surface of a layer of polysilicon from which the bottom electrode is formed. Still another approach is taught by Liang, et al., in U.S. Pat. No. 5,714,412 for forming a multi-level, split-gate flash memory cell where a control gate spans a pair of floating gate electrodes. A method of programming a flash memory cell is taught by Bergemont of U.S. Pat. No. 5,464,999.
In the present invention, a differently shaped floating gate is disclosed for improving the coupling between the floating gate and control gate of a stacked-gate flash memory cell. The method employed is applicable for increasing the coupling ratio of the well-known Intel ETOX (EPROM with tunnel oxide) memory cell, as shown later in the embodiments of the present invention.